The operation of most digital circuit systems, such as computer systems, is synchronized by a periodic signal known as a “clock” that dictates the sequence and pacing of the devices of the circuit. Often, this clock is distributed from a single source to all the memory elements of the circuit, which are also called registers, latches, flip-flops, or memories. In a circuit using edge-triggered flip-flops, when the clock edge or tick arrives at a flip-flop, the flip-flop transfers the flip-flop input to the flip-flop output, and these new output values flow through combinational logic to provide the values at a next flip-flop's inputs for the next clock tick.
Ideally, the input to each memory element reaches its final value to be computed in time for the next clock tick so that the behavior of the whole circuit can be predicted exactly. The maximum speed or clock frequency at which a system may run generally accounts for the variance that occurs between the various elements of a circuit due to differences in physical composition, temperature, and path length.
In circuit designs, clock skew (sometimes called timing skew) is a phenomenon in synchronous circuits in which the clock signal (sent from the clock circuit) arrives at different components at different times. Occasionally, this may be caused by many different things, such as wire-interconnect length, temperature variations, variation in intermediate devices, capacitive coupling, material imperfections, differences in input capacitance on the clock inputs of devices using the clock, random and systemic variation and clock jitter, etc. As the clock rate of a circuit increases, timing becomes more critical and less variation can be tolerated if the circuit is to function properly.
Generally, there are two types of clock skew: negative latency (pull) and positive latency (push). Positive skew occurs when the receiving flip-flop receives the clock tick later than the sending flip-flop. Negative skew is the opposite: the receiving register gets the clock tick earlier than the sending register. Zero clock skew refers to the arrival of the clock tick substantially simultaneously at transmitting and receiving register.